The field of the present invention is digital counters, and more particularly, multiple input parallel counters, and still more particularly, generalized 7/3 counters useful for array multipliers and other matrix operations where rows of numbers are to be added in parallel.
Counters are used in place of 2/1 adders for applications that need to add many operands together. They provide a means of avoiding the carry propagation of a carry lookahead adder(CLA) thus reducing the number of operands to be added in a reduced number of stages. This is because in a 3/2 counter 3 operands are reduced to 2 operands bitwise and they do not require a carry to be propagated the length of the operand. In most applications where many operands must be summed, counters are used to reduce the operands to 2 operands and then a CLA is used to reduce two operands to the final sum. Various applications exist for these counters, for example in multipliers where many partial products must be reduced to the final product. Dadda, Some Schemes for Parallel Multipliers, Alta Frequenza, Vol. 34, pp. 349-356 (May 1965), Dadda, Composite Parallel Counters, IEEE Trans. Comput., Vol. C-29, pp. 942-946 (Oct. 1965) and Wallace, A Suggestion For a Fast Multiplier, IEEE Trans. Electron Comput., Vol. EC-13, pp. 14-17 (Feb. 1964), have suggested optimal layouts for these counters to reduce the number of counter books and stages required for the reduction of partial products in multipliers. In addition, generalized 3/2 counters for two's complement multipliers have been suggested by Pezaris, A 40-ns 17-Bit Array Multiplier, IEEE Trans. Comput., Vol. C-20, pp. 442-447 (Apr. 1971).
3/2 counters have been used in many implementations. See George and Hefner, High Speed Hardware Multipilier For Fixed Floating Point Coerands. U.S. Pat. No. 4,594,679 (June 10, 1986); Baugh and Wooley, A Two's Complement Parallel Array Multiplication Algorithm, IEEE Trans. Comput., Vol. C-22, pp. 1045-1047 (Dec. 1973); and Hwang, Computer Arithmetic Principles, Architecture, and Design, pp. 173-176 (1979). 7/3 counters, however, have been avoided due to the complexity associated with their design. The design complexity of the 7/3 counter is principally a result of difficulties presented by the primary carry bit. In this regard, the counter produces 3 output bits: the sum bit, the least significant which by placement is multiplied by 2.sup.0, the primary carry bit, the middle in significance which by placement has an implied multiplication by 2.sup.1, and the secondary carry bit, the most significant and has implied multiplication of 2.sup.2. The sum bit is equal to one if the sum of the input elements is odd which can easily be implemented by a 7 way exclusive-O-Ring (XOR). The secondary carry bit is equal to one if the sum of the elements is equal to 4 or more; to implement this in one stage would require 4.times.35 AND-OR (AO) gate. Two stages would require 35 4-way NAND gates, wire-ANDing capability of 35 inputs, and an inverter. Three stages with wire-ANDing could be done by 5 8-way ANDs and the inversion by a 5 way NAND. The primary carry bit is more difficult to implement than either the sum bit or the secondary carry, it is equal to a one if the sum is equal to 2, 3, 6, or 7. To implement this bit from all the combinations that produce these sums would require a 7.times.64 AO. With minimization this gate is reduced to a 6.times.48 AO which can't be implemented very easily especially compared to the 4.times.35 AO required for the secondary carry bit In addition both the true and complement of the inputs are required and their fanouts would require repowering stages.
A 7/3 counter employing a small, fast architecture would be desirable. Such counters would result in the advantage of fewer stages required for the reductions. For instance in 7 stages, using 3/2 counters and 1 CLA, 19 terms can be reduced to 1; in 7 stages, using 7/3 counters, 1 - 3/2 counter, and 1 CLA, 183 terms can be reduced to 1. In addition, 35 terms can be reduced to 1 in 5 stages, 15 terms can be reduced to 1 in 4 stages and 7 terms can be reduced to 1 in 3 stages, using a 7/3 counter scheme. In general, it can be stated that 7/3 counters inherently require fewer stages to reduce the same number of terms.